Traditionally, high temperature C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a substrate with the most common and widely utilized package being an organic laminate. Conventionally, the C4 bumps (solder bumps) are made from leaded solder, as it has superior properties. For example, lead is known to mitigate thermal coefficient (TCE) mismatch between the chip and the substrate (i.e., organic laminate). Accordingly, stresses imposed during the cooling cycle are mitigated by the C4 bumps, thus preventing delaminations or other damage from occurring to the chip or the substrate.
Lead-free requirements are now being imposed by many countries forcing manufacturers to implement new ways to produce chip to substrate joints. For example, solder interconnects consisting of tin/copper, tin/silver (with high concentrations of silver) and tin/gold in combination with SAC alloys are being used as a replacement for the leaded solder interconnents. With lead-free requirements, though, concerns about electromigration (EM) in C4 interconnections have resurfaced. This is mainly due to the migration to Sn based, Pb-free, solders and of the simultaneous demand for finer pitch interconnections with higher current densities.
Illustratively, during the chip joining reflow, the chip and its substrate are heated to an elevated temperature (about 250° C.) in order to form the solder interconnection joints. The initial portion of the cool down leads to little stress build up; however, as the joints solidify (around 180° C. for small lead-free joints), increased stress is observed on the package. In particular, as the package (laminate, solder and chip) begins to cool, the solder begins to solidify (e.g., at about 180° C.) and the laminate begins to shrink as the chip remains substantially the same size. The difference in thermal expansion between the chip and the substrate is accommodated by out-of-plane deformation (warpage) of the device and the substrate, and by the shear deformation of the solder joints. The peak stresses on the device occur during the cool down portion of the reflow. The warpage and peak stresses are shown graphically in FIG. 1.
As the solder is robust and exceeds the strength of the chip, tensile stresses begin to delaminate structures on the chip. The high shear stresses caused by the TCE mismatch between the chip (3.5 ppm) and the laminate (16 ppm) results in an interfacial failure (i.e., a separation between the BEOL copper and the dielectric under the C4) within the semiconductor device. That is, cracks in chip metallurgy under C4 bumps have been observed (named “white bumps” due to their appearance in CSAM inspection processes) which lead to failure of the device. This is shown representatively in FIG. 2.
With increasingly brittle semiconductor devices at the 65 nm technology node and beyond, and with lead-free alloys which are more resistant to deformation than their leaded counterparts, the assembly process itself can generate sufficient stress to damage the device. Since the stresses and temperature ranges during assembly differ from normal operation of the device, the engineering of a robust assembly process which enables the packaging of the most advanced semiconductor devices requires the proper understanding of the mechanical behaviour of lead-free solder joints. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.